1. Field of the Invention
The present invention relates to semiconductor circuit manufacturing and, more specifically, to fabricating copper interconnects in an integrated circuit.
2. Discussion of the Related Art
The active devices of an integrated circuit are interconnected through the use of multilevel interconnects to form functional circuits and components. An example of a technique of forming such interconnects in a multilevel-interconnect system is shown in FIGS. 1 and 2.
FIG. 1 shows an aluminum layer 14 blanket deposited over a silicon dioxide layer 12 which is deposited over a substrate 10. Aluminum layer 14 is then etched by using conventional photolithography to form interconnects 16, as shown in FIG. 2.
Copper is a better conductor material than aluminum because of a lower resistivity, thus allowing higher current densities. Copper also shows a better electromigration resistance. However, copper cannot be etched conventionally. Copper damascene technology has thus been developed for forming copper interconnects.
A conventional copper damascene process is described in reference to FIGS. 3 through 7. FIG. 3 shows a dielectric layer 32 deposited over a substrate 30. Dielectric layer 32 is then etched using conventional photolithography to form trenches 34, as shown in FIG. 4. FIG. 5 shows a diffusion barrier 36 formed over dielectric layer 32 and into trenches 34. Next, a copper layer 38 is deposited over diffusion barrier 36, as shown in FIG. 6.
FIG. 7 shows removal of metals by chemical mechanical polishing (CMP) from dielectric layer 32, except from trenches 34, and formation of interconnects 40 and 41. The portion of diffusion barrier 36 on top of dielectric layer 32 is also removed during the copper CMP process. Because the CMP rate for copper is three times or more higher than the CMP rate for diffusion barrier 36, a phenomenon called dishing results, as shown at the top surfaces of interconnects 40 and 41. Dishing is said to occur when the interconnects exhibit varied topography, e.g., in cross section 44 of interconnect 40, outer edges 43 have higher topography than central portion 45. Dishing is undesirable because thinner copper lines cause undesirable higher current density.
An additional problem caused by polishing off the portion of diffusion barrier 36 on top of dielectric layer 32 during the CMP process is heavy oxidation of the top surface of remaining copper layer 38 due to the oxidizing effect of CMP chemistry, and copper exposure to air. The oxidized copper undesirably increases via resistance. A further concern is contamination of dielectric layer 32 after the portion of diffusion barrier 36 on top of dielectric layer 32 is polished off because copper tends to migrate into the exposed dielectric layer 32.
FIGS. 8 through 12 illustrate double damascene technology which is an extension of the copper damascene process described above. FIG. 8 shows a dielectric layer 48, a nitride layer 50, and a dielectric layer 52 deposited in sequence over the structure of FIG. 7.
A resist (not shown) is deposited and patterned to define contact regions. Dielectric layer 48, nitride layer 50 and second dielectric layer 52 are then etched to form vias 54, as shown in FIG. 9. The resist is removed. A second resist (not shown) is deposited and patterned to define interconnect regions. Dielectric layer 52 is etched selectively with respect to nitride layer 50, forming trenches 56, as shown in FIG. 10. FIG. 11 shows a diffusion barrier 58 blanket deposited over the structure of FIG. 10 and into vias 54 and trenches 56. A copper layer 60 is then deposited over diffusion barrier 58.
FIG. 12 shows formation of interconnects 62 and 63 after CMP and the resulting dishing shown by regions 64 and 66, respectively. Interconnects 62 and 63 exhibit worse dishing than that of interconnects 40 and 41, respectively, due to the cumulative effect of dishing. The accumulated dishing causes significant variation in subsequent damascene structure as more metal layers are formed. As a consequence, the aspect ratio, which is defined as the width over the height of the vias, decreases, thereby reducing the process window.
What is needed is a method to fabricate a copper interconnect which does not exhibit dishing, oxidized copper and contaminated dielectric.